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3.1 nv/hz, 1 ma, 180 mhz, rail-to-rail input/output amplifiers data sheet ada4807-1 / ada4807-2 / ADA4807-4 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2014C2015 analog devices, inc. all rights reserved. technical support www.analog.com features low input noise 3.1 nv/hz at f = 100 khz with 29 hz 1/f corner 0.7 pa/hz at f = 100 khz with 2 khz 1/f corner high speed performance with dc precision 180 mhz, ?3 db bandwidth (g = +1, v out = 20 mv p-p) 225 v/s slew rate for 5 v step (rise) 47 ns settling time to 0.1% for 4 v step 125 v and 3.7 v/c maximum input offset voltage and drift 100 na and 250 pa/c maximum in put offset current and drift low distortion (hd2/hd3), v s = 5 v, v out = 2 v p-p ?141 dbc/?144 dbc at 1 khz ?112 dbc/?115 dbc at 100 khz ?95 dbc/?79 dbc at 1 mhz low power operation 1.0 ma quiescent supply current per amplifier at 5 v dynamic power scaling fully specified at +3 v, +5 v, and 5 v supplies rail-to-rail inputs and outputs applications high resolution analog-to-digital converter (adc) drivers portable and battery-powered instruments and systems high component density data acquisition systems audio signal conditioning active filters pin connection diagrams v out 1 ?v s 2 +in 3 +v s 6 disable 5 ?in 4 12611-001 figure 1. 6-lead sc70 and 6-lead sot-23 pin configuration ( ada4807-1 ) v out1 1 ?in1 2 +in1 3 ?v s 4 +v s 8 v out2 7 ?in2 6 +in2 5 12611-058 figure 2. 8-lead msop pin configuration ( ada4807-2 ) 1v out1 2 ?in1 3 +in1 4 ?v s 5 disable1 10 +v s 9v out2 8?in2 7+in2 6 disable2 12611-059 figure 3. 10-lead lfcsp pin configuration ( ada4807-2 ) +v s +in2 v out2 v out4 +in4 ?v s +in3 v out3 +in1 v out1 1 2 3 4 5 6 7 14 13 12 11 10 9 8 ?in1 ?in2 ?in4 ?in3 ADA4807-4 12611-104 figure 4. 14-lead tssop pin configuration ( ADA4807-4 ) general description the ada4807-1 (single), ada4807-2 (dual), and ADA4807-4 (quad) are low noise, rail-to-rail input and output, voltage feedback amplifiers. these amplifiers combine low power, low noise, high speed, and dc precision to provide an attractive solution for a wide range of applications from high resolution data acquisition instrumentation to high performance battery- powered and high component density systems where power consumption is of key importance. with only 1.0 ma of supply current per amplifier, the ada4807-1 / ada4807-2 / ADA4807-4 feature the lowest input voltage noise among high speed, rail-to-rail input/output amplifiers in the industry and offer a wide bandwidth, high slew rate, fast settling time, and excellent distortion performance. additionally, these amplifiers offer very low input offset voltage and drift performance, making them ideal for driving multiplexed and high throughput precision 16-/18-bit successive approximation registers (sars) and 24-bit ? - ? adcs. these amplifiers are fully specified at +3 v, +5 v, and 5 v supplies and can operate over the industrial ?40c to +125c temperature range. the ada4807-1 is available in 6-lead sot-23 and space-saving 6-lead sc70 packages. the ada4807-2 is available in an 8-lead msop and a compact, 3 mm 3 mm, 10-lead lfcsp. the ADA4807-4 is available in a 14-lead tssop package. table 1. other rail-to-rail amplifiers device bandwidth (mhz) slew rate (v/s) voltage noise (nv/hz) max. v os (mv) ad8031/ ad8032 80 35 15 1.5 ad8027/ ad8028 190 90 4.3 0.8 ad8029 / ad8030 / ad8040 125 62 16.5 5
ada4807-1/ada4807-2/ADA4807-4 data sheet rev. b | page 2 of 33 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? pin connection diagrams ............................................................... 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? 5 v supply ................................................................................... 3 ? 5 v supply ...................................................................................... 5 ? 3 v supply ...................................................................................... 7 ? absolute maximum ratings ............................................................ 9 ? maximum power dissipation ..................................................... 9 ? thermal resistance ...................................................................... 9 ? esd caution .................................................................................. 9 ? pin configurations and function descriptions ......................... 10 ? typical performance characteristics ........................................... 13 ? frequency response ................................................................... 13 ? frequency and supply current ................................................. 15 ? dc and input common-mode performance ......................... 16 ? slew, transient, settling time, and crosstalk ............................. 18 ? distortion and noise .................................................................. 20 ? output characteristics............................................................... 22 ? overdrive recovery and turn on/turn off times .............. 23 ? theory of operation ...................................................................... 24 ? disable circuitry ........................................................................ 25 ? input protection ......................................................................... 25 ? noise considerations ................................................................. 25 ? applications information .............................................................. 26 ? capacitive load drive ............................................................... 26 ? low noise fet operational amplifier ................................... 26 ? power mode adc driver ......................................................... 27 ? adc driving ............................................................................... 28 ? adc driving with dynamic power scaling ........................... 29 ? layout, grounding, and bypassing .......................................... 30 ? outline dimensions ....................................................................... 31 ? ordering guide .......................................................................... 33 ? revision history 9/15rev. a to rev. b added ADA4807-4 ............................................................. universal changes to features section, general description section, and table 1 .......................................................................................................... 1 added figure 4, renumbered sequentially .................................. 1 changes to table 2 ............................................................................ 3 changes to table 3 ............................................................................ 5 changes to table 4 ............................................................................ 7 deleted figure 6, renumbered sequentially ............................... 10 changes to figure 6 ........................................................................ 10 added figure 9 and table 9, renumbered sequentially ........... 12 changes to figure 20 ...................................................................... 14 added figure 21 .............................................................................. 14 added figure 31 and figure 32..................................................... 16 added figure 35 .............................................................................. 17 changes to figure 39 ...................................................................... 18 added figure 42 .............................................................................. 19 deleted figure 50, figure 51, figure 53, and figure 54 ............. 19 added figure 46 .............................................................................. 20 added figure 49 and figure 51..................................................... 21 added figure 59 and figure 61..................................................... 23 changes to disable circuitry section ...................................... 25 added low noise fet operational amplifier section ............. 26 added figure 70, figure 71, figure 72, and power mode adc driver section ................................................................................. 27 added adc driving section and figure 73 through figure 77 ..... 28 added adc driving with dynamic power scaling section, figure 78, figure 79, and figure 80 .............................................. 29 added figure 58 ............................................................................. 33 changes to ordering guide .......................................................... 33 4/15rev. 0 to rev. a added ada4807-2 ............................................................. universal changes to features section, general description section, and pin connection diagrams heading ......................... 1 added figure 2 and figure 3; renumbered sequentially ............ 1 changes to table 1 ............................................................................. 3 changes to table 2 ............................................................................. 5 changes to table 3 ............................................................................. 7 changes to table 6 and figure 4 ...................................................... 9 added figure 7, figure 8, and table 8; renumbered sequentially .... 11 reorganized layout, typical performance characteristics section .............................................................................................. 12 added figure 36 ............................................................................. 16 changes to figure 37 caption, figure 38 caption, figure 39 caption, and figure 40 caption ................................................... 17 changes to figure 44 and figure 47............................................. 18 change to theory of operation section ..................................... 20 changes to disable circuitry section, table 9, and noise considerations section .................................................................. 21 added figure 65 and figure 66 .................................................... 23 changes to ordering guide .......................................................... 25 12/14revision 0: initial version
data sheet ada4807-1/ada4807-2/ADA4807-4 rev. b | page 3 of 33 specifications 5 v supply t a = 25c, v s = 5 v, r load = 1 k to midsupply, r f = 0 , g = +1, ?v s v icm +v s ? 1.5 v, unless otherwise noted. table 2. parameter test conditions/comments min typ max unit dynamic performance C3 db bandwidth g = +1, v out = 20 mv p-p 180 mhz g = +1, v out = 2 v p-p 28 mhz slew rate g = +1, v out = 5 v step, 20% to 80%, rise/fall 225/250 v/s settling time to 0.1% g = +1, v out = 4 v step 47 ns distortion/noise performance second harmonic (hd2) f c = 1 khz, v out = 2 v p-p ?141 dbc f c = 100 khz, v out = 2 v p-p ?112 dbc f c = 1 mhz, v out = 2 v p-p, ada4807-1 ?95 dbc f c = 1 mhz, v out = 2 v p-p, ada4807-2 , ADA4807-4 ?84 dbc third harmonic (hd3) f c = 1 khz, v out = 2 v p-p ?144 dbc f c = 100 khz, v out = 2 v p-p ?115 dbc f c = 1 mhz, v out = 2 v p-p ?79 dbc peak-to-peak noise f = 0.1 hz to 10 hz 160 nv p-p input voltage noise f = 100 khz 3.1 nv/hz f = 1 khz 3.3 nv/hz f = 10 hz 5.8 nv/hz input voltage noise 1/f corner 29 hz input current noise f = 100 khz 0.7 pa/hz f = 10 hz 10 pa/hz input current noise 1/f corner 2 khz dc performance input offset voltage ?v s v icm +v s ? 1.5 v ada4807-1 , ada4807-2 ?125 20 +125 v ADA4807-4 ?175 20 +175 v +v s ? 1.5 v v icm +v s ada4807-1 , ada4807-2 ?750 140 +750 v ADA4807-4 ?850 140 +850 v input offset voltage drift ?v s v icm +v s ? 1.2 v, t min to t max 0.7 3.7 v/c input bias current ?v s v icm +v s ? 1.5 v ?1.2 ?1.6 a +v s ? 1.5 v v icm +v s 530 1000 na input bias current drift ?v s v icm +v s ? 1.2 v, t min to t max 2.5 3.6 na/c input offset current ?v s v icm +v s ? 1.5 v 8 100 na +v s ? 1.5 v v icm +v s 25 150 na input offset current drift ?v s v icm +v s ? 1.2 v, t min to t max 30 250 pa/c open-loop gain 120 130 db input characteristics common-mode input resistance 45 m differential input resistance 35 k common-mode input capacitance 1 pf differential input capacitance 1 pf input common-mode voltage range ?v s ? 0.2 +v s + 0.2 v common-mode rejection ratio (cmrr) v icm = ?3 v to +2 v 96 110 db
ada4807-1/ada4807-2/ADA4807-4 data sheet rev. b | page 4 of 33 parameter test conditions/comments min typ max unit disable characteristics 1 disable input voltage 2 low disabled <1.3 v high enabled >1.7 v disable input current low disabled ?470 na high enabled ?3 na disable on time disable input midswing point to >90% of final v out , v pd = +v s 1.3 1.8 s disable off time disable input midswing point to <10% of enabled quiescent current, v pd = ?v s 270 340 ns output characteristics saturated output voltage swing r load = 1 k high +v s ? 0.08 +v s ? 0.04 v low ?v s + 0.1 ?v s + 0.07 v linear output current 3 sourcing, g = +1, v in = +v s , r load = varied 50 ma sinking, g = +1, v in = ?v s , r load = varied 60 ma short-circuit current sourcing, g = +1, v in =+v s , r load = 0 to 10 80 ma sinking, g= +1, v in = ?v s , r load = 0 to 10 80 ma capacitive load drive c load = 15 pf, v out = 20 mv p-p 17 % overshoot power supply operating range 2.7 11 v quiescent current per amplifier enabled, no load, t a = 25c 1.0 1.1 ma disabled, t a = 25c 2.4 4.0 a power supply rejection ratio (psrr) positive +v s = 3 v to 5 v, ?v s = ?5 v 98 107 db negative +v s = 5 v, ?v s = ?3 v to ?5 v 98 120 db 1 the disable pin is disable on the ada4807-1 and disable1 or disable2 for the ada4807-2 lfcsp package, hereafter referred to as disable for the ada4807-1 / ada4807-2 . 2 see the disable circuitry section. 3 see figure 53 and figure 56.
data sheet ada4807-1/ada4807-2/ADA4807-4 rev. b | page 5 of 33 5 v supply t a = 25c, v s = 5 v, r load = 1 k to midsupply, r f = 0 , g = +1, 0 v v icm +v s ? 1.5 v, unless otherwise noted. table 3. parameter test conditions/comments min typ max unit dynamic performance C3 db bandwidth g = +1, v out = 20 mv p-p 170 mhz g = +1, v out = 2 v p-p 28 mhz slew rate g = +1, v out = 2 v step, 20% to 80%, rise/fall 145/160 v/s settling time to 0.1% g = +1, v out = 2 v step 40 ns distortion/noise performance second harmonic (hd2) f c = 1 khz, v out = 2 v p-p ?141 dbc f c = 100 khz, v out = 2 v p-p ?111 dbc f c = 1 mhz, v out = 2 v p-p, ada4807-1 ?93 dbc f c = 1 mhz, v out = 2 v p-p, ada4807-2 , ADA4807-4 ?83 dbc third harmonic (hd3) f c = 1 khz, v out = 2 v p-p ?153 dbc f c = 100 khz, v out = 2 v p-p ?115 dbc f c = 1 mhz, v out = 2 v p-p ?78 dbc peak-to-peak noise f = 0.1 hz to 10 hz 160 nv p-p input voltage noise f = 100 khz 3.1 nv/hz f = 1 khz 3.3 nv/hz f = 10 hz 5.8 nv/hz input voltage noise 1/f corner 29 hz input current noise f = 100 khz 0.7 pa/hz f = 10 hz 10 pa/hz input current noise 1/f corner 2 khz dc performance input offset voltage 0 v v icm +v s ? 1.5 v ada4807-1 , ada4807-2 ?125 20 +125 v ADA4807-4 ?175 20 +175 v +v s ? 1.5 v v icm +v s ada4807-1 , ada4807-2 ?720 110 +720 v ADA4807-4 ?850 110 +850 v input offset voltage drift 0 v v icm +v s ? 1.2 v, t min to t max 0.7 3.7 v/c input bias current 0 v v icm +v s ? 1.5 v ?1.2 ?2.0 a +v s ? 1.5 v v icm +v s 500 1000 na input bias current drift 0 v v icm +v s ? 1.2 v, t min to t max 2.6 3.8 na/c input offset current 0 v v icm +v s ? 1.5 v 8 100 na +v s ? 1.5 v v icm +v s 25 150 na input offset current drift 0 v v icm +v s ? 1.2 v, t min to t max 30 250 pa/c open-loop gain 113 130 db input characteristics common-mode input resistance 45 m differential input resistance 35 k common-mode input capacitance 1 pf differential input capacitance 1 pf input common-mode voltage range ?v s ? 0.2 +v s + 0.2 v cmrr v icm = 1 v to 3 v 96 110 db
ada4807-1/ada4807-2/ADA4807-4 data sheet rev. b | page 6 of 33 parameter test conditions/comments min typ max unit disable characteristics 1 disable input voltage 2 low disabled <1.3 v high enabled >1.8 v disable input current low disabled ?360 na high enabled ?1.3 na disable on time disable input midswing point to >90% of final v out , v pd = +v s 450 700 ns disable off time disable input midswing point to <10% of enabled quiescent current, v pd = ?v s 270 450 ns output characteristics saturated output voltage swing r load = 1 k high +v s ? 0.05 +v s ? 0.03 v low ?v s + 0.05 ?v s + 0.04 v linear output current 3 sourcing, g = +1, v in = +v s , r load = varied 50 ma sinking, g = +1, v in = ?v s , r load = varied 60 ma short-circuit current sourcing, g = +1, v in = +v s , r load = 0 to 10 80 ma sinking, g = +1, v in = ?v s , r load = 0 to 10 80 ma capacitive load drive c load = 15 pf, v out = 20 mv p-p 24 % overshoot power supply operating range 2.7 11 v quiescent current per amplifier enabled, no load, t a = 25c 950 1000 a disabled, t a = 25c 1.3 2.0 a psrr positive +v s = 1.5 v to 3.5 v, ?v s = ?2.5 v 98 115 db negative +v s = 2.5 v, ?v s = ?1.5 v to ?3.5 v 98 130 db 1 the disable pin is disable on the ada4807-1 and disable1 or disable2 for the ada4807-2 lfcsp package, hereafter referred to as disable for the ada4807-1 / ada4807-2 . 2 see the disable circuitry section. 3 see figure 53 and figure 56.
data sheet ada4807-1/ada4807-2/ADA4807-4 rev. b | page 7 of 33 3 v supply t a = 25c, v s = 3 v, r load = 1 k to midsupply, r f = 0 , g = +1, 0 v v icm +v s ? 1.5 v, unless otherwise noted. table 4. parameter test conditions/comments min typ max unit dynamic performance C3 db small signal bandwidth g = +1, v out = 20 mv p-p 165 mhz g = +1, v out = 2 v p-p 28 mhz slew rate g = +1, v out = 2 v step, 20% to 80%, rise/fall 118/237 v/s settling time to 0.1% g = +1, v out = 2 v step 40 ns distortion/noise performance second harmonic (hd2) f c = 1 khz, v out = 2 v p-p ?98 dbc f c = 100 khz, v out = 2 v p-p ?85 dbc f c = 1 mhz, v out = 2 v p-p ?65 dbc third harmonic (hd3) f c = 1 khz, v out = 2 v p-p ?94 dbc f c = 100 khz, v out = 2 v p-p ?91 dbc f c = 1 mhz, v out = 2 v p-p ?68 dbc peak-to-peak noise f = 0.1 hz to 10 hz 160 nv p-p input voltage noise f = 100 khz 3.1 nv/hz f = 10 khz 3.3 nv/hz f = 10 hz 5.8 nv/hz input voltage noise 1/f corner 29 hz input current noise f = 100 khz 0.7 pa/hz f = 10 hz 10 pa/hz input current noise 1/f corner 2 khz dc performance input offset voltage 0 v v icm +v s ? 1.5 v ada4807-1 , ada4807-2 ?125 20 +125 v ADA4807-4 ?175 20 +175 v +v s ? 1.5 v v icm +v s ada4807-1 , ada4807-2 ?720 125 +720 v ADA4807-4 ?850 125 +850 v input offset voltage drift 0 v v icm +v s ? 1.2 v, t min to t max 0.7 3.8 v/c input bias current 0 v v icm +v s ? 1.5 v ?1.2 ?2.0 a +v s ? 1.5 v v icm +v s 500 1000 na input bias current drift 0 v v icm +v s ? 1.2 v, t min to t max 2.7 3.8 na/c input offset current 0 v v icm +v s ? 1.5 v 8 130 na +v s ? 1.5 v v icm +v s 25 150 na input offset current drift 0 v v icm +v s ? 1.2 v, t min to t max 40 230 pa/c open-loop gain 104 113 db input characteristics common-mode input resistance 45 m differential input resistance 35 k common-mode input capacitance 1 pf differential input capacitance 1 pf input common-mode voltage range ?v s ? 0.2 +v s + 0.2 v cmrr v icm = 0.3 v to 1.3 v 92 110 db
ada4807-1/ada4807-2/ADA4807-4 data sheet rev. b | page 8 of 33 parameter test conditions/comments min typ max unit disable characteristics 1 disable input voltage 2 low disabled <1.1 v high enabled >1.5 v disable input current low disabled ?325 na high enabled ?500 na disable on time disable input midswing point to >90% of final v out , v pd = +v s 500 700 ns disable off time disable input midswing point to <10% of enabled quiescent current, v pd = ?v s 270 460 ns output characteristics saturated output voltage swing r load = 1 k high +v s ? 0.04 +v s ? 0.02 v low ?v s + 0.04 ?v s + 0.03 v linear output current 3 sourcing, g = +1, v in = +v s , r load = varied 50 ma sinking, g = +1, v in = ?v s , r load = varied 60 ma short-circuit current sourcing, g = +1, v in = +v s , r load = 0 to 10 65 ma sinking, g = +1, v in = ?v s , r load = 0 to 10 70 ma capacitive load drive c load = 15 pf, v out = 20 mv p-p 30 % overshoot power supply operating range 2.7 11 v quiescent current per amplifier enabled, no load, t a = 25c 915 1000 a disabled, t a = 25c 1.0 2.0 a psrr positive +v s = 1.5 v to 3.5 v, ?v s = ?1.5 v 97 113 db negative +v s = 1.5 v, ?v s = ?1.5 v to ?3.5 v 97 130 db 1 the disable pin is disable on the ada4807-1 and disable1 or disable2 for the ada4807-2 lfcsp package, hereafter referred to as disable for the ada4807-1 / ada4807-2 . 2 see the disable circuitry section. 3 see figure 53 and figure 56.
data sheet ada4807- 1/ada4807 - 2/ada4807 - 4 rev. b | page 9 of 33 absolute maximum rat ings table 5 . parameter rating supply voltage 11 v internal power dissipation see figure 5 input voltage (common mode) v s 0.2 v differential input voltage 1.4 v output short - circuit duration see power derating curves in figure 5 storage temperature range (all packages) ?65c to +125c lead temperature (soldering 10 s ec) 300c stresses at or above those listed under absolute maximum ratings may cause permanent da mage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. maximum power dissip ation the m aximum power that can be safely dissipated by the ada4807 - 1 / ada4807 - 2 / ada4807 - 4 is limited by the associated ri se in junction temperature. the maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150c . exceeding this limit temporarily can cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of 175c for an extended period can result in device failure. although the ada4807 - 1 / ada4807 - 2 / ada4807 - 4 are internally short - circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150c) is not exceeded under all conditions. to ensure p ro per operation, it is necessary to observe the power derati ng curves shown in figure 5 . thermal resistance ja is specified for the worst case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 6 . thermal resistance package type ja unit 6 - lead sc70, 4- layer board 209 c/w 6 - lead sot - 23, 4 - layer board 223 c/w 8 - lead msop 123 c/w 10- lead lfcsp 51 c/w 14- lead tssop 130 c/w ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 maximum power dissi pa tion (w) ambient temper a ture (c) sot -23 tsso p msop lfcs p sc70 126 1 1-003 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 figure 5 . maximum power dissipation vs. ambient temperature for a 4- layer board esd caution
ada4807-1/ada4807-2/ADA4807-4 data sheet rev. b | page 10 of 33 pin configurations and function descriptions v out 1 ?v s 2 +in 3 +v s 6 disable 5 ?in 4 12611-004 figure 6. ada4807-1 pin configuration table 7. ada4807-1 pin function descriptions pin no. mnemonic description 1 v out output 2 ?v s negative supply 3 +in noninverting input 4 ?in inverting input 5 disable active low power-down 6 +v s positive supply
data sheet ada4807-1/ada4807-2/ADA4807-4 rev. b | page 11 of 33 1v out1 2 ?in1 3 +in1 4 ?v s 5 disable1 10 +v s notes 1. the exposed pad can be connected to ground or power planes, or it can be left floating. 9v out2 8?in2 7+in2 6 disable2 12611-060 figure 7. ada4807-2 10-lead lfcsp pin configuration v out1 1 ?in1 2 +in1 3 ?v s 4 +v s 8 v out2 7 ?in2 6 +in2 5 12611-061 figure 8. ada4807-2 8-lead msop pin configuration table 8. ada4807-2 pin function descriptions pin no. 10-lead lfcsp 8-lead msop mnemonic description 1 1 v out1 output 1. 2 2 ?in1 inverting input 1. 3 3 +in1 noninverting input 1. 4 4 ?v s negative supply. 5 not applicable disable1 active low power-down 1. 6 not applicable disable2 active low power-down 2. 7 5 +in2 noninverting input 2. 8 6 ?in2 inverting input 2. 9 7 v out2 output 2. 10 8 +v s positive supply. not applicable epad exposed pad. for the 10-lead lfcsp, the exposed pad can be connected to ground or power planes, or it can be left floating.
ada4807-1/ada4807-2/ADA4807-4 data sheet rev. b | page 12 of 33 +v s +in2 v out2 v out4 +in4 ?v s +in3 v out3 +in1 v out1 1 2 3 4 5 6 7 14 13 12 11 10 9 8 ?in1 ?in2 ?in4 ?in3 ADA4807-4 12611-110 figure 9. ADA4807-4 pin configuration table 9. ADA4807-4 pin function descriptions pin no. mnemonic description 1 v out1 output 1 2 ?in1 inverting input 1 3 +in1 noninverting input 1 4 +v s positive supply 5 +in2 noninverting input 2 6 ?in2 inverting input 2 7 v out2 output 2 8 v out3 output 3 9 ?in3 inverting input 3 10 +in3 noninverting input 3 11 ?v s negative supply 12 +in4 noninverting input 4 13 ?in4 inverting input 4 14 v out4 output 4
data sheet ada4807- 1/ada4807 - 2/ada4807 - 4 rev. b | page 13 of 33 typical performance characteristics frequency response g = +1 ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 6 9 12 15 18 21 24 27 0.1 1 10 100 1000 closed-loop gain (db) frequency (mhz) g = +10 g = +5 g = +2 v s = 2.5v r load = 1k? v out = 20mv p-p g = ?1 12611-006 figure 10 . small signal frequency response for various gains, r f = 499 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 6 0.1 1 10 100 1000 closed-loop gain (db) frequency (mhz) v out = 20mv p-p g = +1 r load = 1k? 1.5v 5.0v 2.5v 12611-007 figure 11 . small signal frequency response for various supplies ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 6 0.1 1 10 100 1000 closed-loop gain (db) frequenc y (mhz) v s range = 1.5v t o 5v g = +1 v out = 20mv p-p r load = 1k? ?40c +85c +25c +125c 126 1 1-008 figure 12 . small signal frequency response for various temperatures ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 6 0.1 1 10 100 1000 closed-loo p gain (db) frequenc y (mhz) v s range = 2.5v t o 5v g = +1 r load = 1k 200mv p-p 2v p-p 20mv p-p 126 1 1-009 figure 13 . frequency response for various output amplitudes , g = +1 ?30 ?27 ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 6 0.1 1 10 100 1000 closed-loop gain (db) frequency (mhz) v out = 2v p-p g = +1 r load = 1k? 1.5v 5.0v 2.5v 12611-010 figure 14 . large signal frequency response for various supplies ?30 ?27 ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 6 0.1 1 10 100 1000 closed-loo p gain (db) frequenc y (mhz) ?40c v s range = 2.5v to 5v g = +1 v out = 2v p-p r load = 1k? +25c +125c 126 1 1-0 1 1 figure 15 . large signal frequency response for various temperatures
ada4807- 1/ada4807 - 2/ada4807 - 4 data sheet rev. b | page 14 of 33 ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 6 0.1 1 10 100 1000 closed-loop gain (db) frequency (mhz) 1k? 100? v s = 2.5v v out = 20mv p-p g = +1 12611-012 figure 16 . small signal frequency response for various resistive loads 12 ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 6 9 0.1 1 10 100 1000 closed-loop gain (db) frequency (mhz) 12611-050 v s = 2.5v g = +1 v out = 20mv p-p r load = 1k 15pf 10pf 5pf 0pf figure 17 . small signal frequency response for various capacitive loads ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 6 0.1 1 10 1000 100 closed-loo p gain (db) frequency (mhz) v s = 2.5v g = +1 v out = 20mv p-p r load = 1k? v cm = +v s ? 0.5v 12611-013 v cm = 0v figure 18 . small signal frequency response fo r various input common - mode voltages (v cm ) ?30 ?27 ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 6 0.1 1 10 100 1000 closed-loop gain (db) frequency (mhz) v s range = 2.5v to 5v v out = 2v p-p g = +1 1k 100 12611-015 figure 19 . large signal frequency response for various resistive loads ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.1 1 10 100 closed-loo p gain (db) frequenc y (mhz) g = +1 r load = 1k? v s range = 2.5v t o 5v v out = 2v p-p v s range = 1.5v t o 5v v out = 20mv p-p 126 1 1-221 figure 20 . 0.1 db flatness frequency response for various output amplitudes ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 6 0.1 1 10 100 1000 normalized gain (db) frequenc y (mhz) g = 2 r f = 499? r load = 1k? vs = 2.5 v , 5v v out = 200mv p-p vs = 5v v out = 4v p-p vs = 2.5 v , 5v v out = 2v p-p vs = 2.5 v , 5v v out = 20mv p-p 126 1 1-121 figure 21 . frequency response for various output amplitudes, g = +2
data sheet ada4807- 1/ada4807 - 2/ada4807 - 4 rev. b | page 15 of 33 frequency and supply current ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 0.01 0.1 1 10 100 1000 off isolation (db) frequency (mhz) on v s = 2.5v g = +1 disable = +v s 12611-017 off disable = ?v s figure 22 . off isolation vs. frequency 0 20 40 60 80 100 120 140 160 ?40 ?20 0 20 40 60 80 100 120 0.001 0.01 0.1 1 10 100 1000 phase (degrees) open-loo p gain (db) frequenc y (mhz) 126 1 1-018 v s = 2.5v figure 23 . open - loop gain and phase vs. frequency 12611-019 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 quiescent supp l y current (ma) temper a ture (c) v s = 1.5v v s = 5.0v v s = 2.5v figure 24 . quiescent supply current vs. temperature 12611-020 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 0.001 0.01 0.1 1 10 100 cmrr (db) frequency (mhz) v s = 2.5v v cm = 0dbm figure 25 . cmrr vs. frequency ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 0.001 0.01 0.1 1 10 100 psrr (db) frequenc y (mhz) ?psrr +psrr v s = 5v v s = ?16dbm 126 1 1-226 figure 26 . psrr vs. frequency ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 0 1 2 3 4 5 6 disable supply current (a) power supply, v s (v) disable = ?v s +i s ?i s 12611-022 figure 27 . disable supply current vs. power supply , v s
ada4807-1/ada4807-2/ADA4807-4 data sheet rev. b | page 16 of 33 dc and input common-mode performance 400 ?600 ?400 ?200 0 input referred offset voltage (v) 200 400 600 350 300 250 numbering units 200 150 100 50 0 v s = 5v v cm = +v s ? 0.5v 450 units x = ?32.7v = 109.4v v s = 5v v cm = 0v 450 units x = ?1.5v = 17.9v 12611-122 npn pnp figure 28. input referred offset voltage distribution for the ada4807-1 and ada4807-2 ?150 ?100 ?50 0 input offset current (na) 50 100 150 300 250 numbering units 200 150 100 50 0 v s = 5v v cm = 0v 450 units x = ?1.58na = 6.62na 12611-123 v s = 5v v cm = +v s ? 0.5v 450 units x = ?1.18na = 22.59na npn pnp figure 29. input offset current distribution 12611-124 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 ? 5.2 ?3.9 ?2.6 ?1.3 0 1.3 2.6 3.9 5.2 input bias current (a) input common-mode voltage (v) v s = 5.0v 10 units figure 30. input bias current vs. input common-mode voltage 0 10 20 30 40 50 60 ?2.8 ?2.2 ?1.6 ?1.0 ?0.4 0.2 0.8 1.4 2.0 2.6 3.2 3.8 number of amplifiers input offset voltage drift (v/c) v s = 2.5v ?40c to +125c count = 361 amplifiers x = 0.7v/c = 0.5v/c 12611-031 figure 31. input referred offset voltage drift distribution, v cm = 0 v 0 10 20 30 40 50 60 70 80 90 ?200 ?140 ?80 ?20 40 100 160 220 280 number of amplifiers input offset current drift (pa/c) v s = 2.5v ?40c to +125c count = 283 amplifiers x = 30pa/c = 35pa/c 12611-032 figure 32. input offset current drift distribution, v cm = 0 v ?30 ?40 ?20 ?10 0 10 20 40 30 ? 5.2 ?3.9 ?2.6 ?1.3 0 1.3 2.6 3.9 5.2 input offset current (na) input common-mode voltage (v) v s = 5.0v 10 units 12611-126 figure 33. input offset current vs. input common-mode voltage
data sheet ada4807- 1/ada4807 - 2/ada4807 - 4 rev. b | page 17 of 33 126 1 1-125 ?300 ?200 ?100 0 100 200 300 ? 5.2 ? 3.9 ? 2.6 ? 1.3 0 1.3 2.6 3.9 5.2 input referred offset vo lt age (v) input common-mode vo lt age (v) v s = 5v 10 units figure 34 . input referred offset voltage vs. input common - mode voltage 10 9 8 7 6 5 4 3 2 1 0 ?4 ?3 ?2 ?1 25 24 23 22 21 20 19 18 17 16 15 1 1 12 13 14 0 100 200 300 400 500 600 changing in input offset vo lt age (v) temper a ture ( c) time (hours) 126 1 1-234 v s = 2.5v 8 units, soldered t o pcb oi l b a th temper a ture figure 35 . long - term input offset voltage ( v os ) drift
ada4807- 1/ada4807 - 2/ada4807 - 4 data sheet rev. b | page 18 of 33 slew, transient , settling time , and crosstalk slew r a te (v/s) 100 120 140 160 180 200 220 240 260 280 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 temper a ture (c) rising edge rising edge f alling edge f alling edge g = +1 r load = 1k v s = 5v v out = 5v p-p v s = 2.5v v out = 2v p-p 126 1 1-023 figure 36 . slew rate vs. temperature ?15 ?10 ?5 0 5 10 15 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 output vo lt age (mv) time (s) g = +1 r load = 1k v s range = 1.5v t o 5v 126 1 1-024 figure 37 . small signal transient response for various supplies 12611-025 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 0 100 200 300 400 500 600 700 800 900 output voltage (v) time (ns) g = +1 r load = 1k? 1.5v 2.5v 5v figure 38 . large signal transient response for various supplies ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 80 90 60 40 20 0 time (ns) output vo lt age (% of final v alue) 126 1 1-238 v s = 5v output ste p = 5v p-p v s = 2.5v output ste p = 2v p-p figure 39 . settling time to 0.1%
data sheet ada4807- 1/ada4807 - 2/ada4807 - 4 rev. b | page 19 of 33 ?15 ?10 ?5 0 5 10 15 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0pf 5pf 10pf 15pf output vo lt age (mv) time (s) v s = 2.5v g = +1 126 1 1-027 figure 40 . small signal transient response for various capacitive loads ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0.0001 0.001 0.01 0.1 1 10 100 1000 cross t alk (db) frequenc y (mhz) v s = 2.5v v out = 2v p-p disable = 2.5v driving am p 1 driving am p 2 126 1 1-036 figure 41 . ada4807 - 2 crosstalk vs. frequency ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100 1k 10k 100k 1m 10m 100m 1g cross t alk (db) frequenc y (hz) v s = 2.5v v out2 , v out3 , v out4 = 1v p-p g = +1 r load = 1k? v out1 126 1 1-241 figure 42 . ada4807 - 4 all hostile crosstalk
ada4807-1/ada4807-2/ADA4807-4 data sheet rev. b | page 20 of 33 distortion and noise ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ? 20 1 10 100 1000 10000 harmonic distortion (dbc) frequency (khz) v s = 1.5v, hd3 v s = 2.5v, hd3 v s = 2.5v, hd2 v s = 5v, hd3 v s = 5v, hd2 v s = 1.5v, hd2 g = +1 r load = 1k ? v out = 2v p-p 12611-127 figure 43. ada4807-1 harmonic distortion vs. frequency for various supplies ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 1 10 100 1000 10000 harmonic distortion (dbc) frequency (khz) v s = 2.5v v out = 2v p-p r load = 1k ? g = +1, hd3 g = +2, hd3 g = +2, hd2 g = +1, hd2 g = +5, hd3 g = +5, hd2 12611-028 figure 44. ada4807-1 harmonic distortion vs. frequency for various gains ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ? 40 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 total harmonic di s tortion (db) v out (v p-p) v s = 2.5v g = +1 r load = 1k ? f = 1khz f = 100khz f = 1mhz 12611-245 figure 45. total harmonic distortion vs. output voltage (v out ) ?170 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0.001 0.01 0.1 1 10 harmonic distortion (dbc) frequency (mhz) hd2 hd3 g = +1 r load = 1k ? v out = 2v p-p v s = 1.5v v s = 2.5v v s = 5v 12611-145 figure 46. ada4807-2 / ADA4807-4 harmonic distortion vs. frequency for various supplies ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ? 20 10 1 100 1000 10000 harmonic distortion (dbc) frequency (khz) g = +1 v out = 2v p-p v s = 2.5v r load = 1k ? hd2 r load = 100 ? hd3 r load = 1k ? hd3 r load = 100 ? hd2 12611-030 figure 47. ada4807-1 harmonic distortion vs. frequency for various resistive loads ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 012345678910 harmonic distortion (dbc) input common-mode voltage (v) v s = 3v v s = 5v v s = 10v hd2 hd3 hd2 hd2 hd3 hd3 g = + 1 v out = 2v p-p r load = 1k ? f = 100khz 12611-037 figure 48. harmonic distortion vs. input common-mode voltage
data sheet ada4807- 1/ada4807 - 2/ada4807 - 4 rev. b | page 21 of 33 0 1 2 3 4 5 6 1 10 100 1000 output vo lt age (v p-p) frequenc y (khz) v s = 2.5v g = +2 r f = 499? r load = 1k? ada4807-1, ada4807-2 ADA4807-4 thd = ?80db thd = ?90db thd = ?100db 126 1 1-248 figure 49 . output voltage vs . frequency for v s = 2.5 v 0.00001 0.0001 0.001 0.01 0.1 1 0.001 0.01 0.1 1 t o t a l harmonic dis t ortion (%) output vo lt age (v rms) 16 32 v s = 2.5v g = +1 f = 1khz 600 126 1 1-132 figure 50 . total harmonic distortion vs. output voltage for various resistive loads 0 2 4 6 8 10 12 1 10 100 1000 output vo lt age (v p-p) frequenc y (khz) v s = 5v g = +2 r f = 499? r load = 1k? 126 1 1-250 ada4807-1, ada4807-2 ADA4807-4 thd = ?80db thd = ?90db thd = ?100db figure 51 . output voltage vs. frequency for v s = 5 v
ada4807-1/ada4807-2/ADA4807-4 data sheet rev. b | page 22 of 33 output characteristics frequency (hz) 0.1 1 10 100 0.1 1 10 100 1 10 100 1k 10k 100k 1m 10m 100m current noise (pa/ hz) input voltage noise (nv/ hz) current noise voltage noise v s range = 1.5v to 5v pnp active 12611-136 figure 52. input voltage noise and current noise vs. frequency, v cm = 0 v 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 102030405060708090100 positive rail output saturation voltage (v) (+v s ? v out ) load current (ma) v s = 2.5v g = +1 12611-040 ?40c +25c +125c +85c figure 53. positive rail output saturation voltage (+v s C v out ) vs. load current for various temperatures 0.01 0.1 1 10 100 1000 0.1 1 10 100 1000 enabled output impedance ( ? ) frequency (mhz) 12611-141 v s = 2.5v disable = +v s figure 54. enabled output impedance vs. frequency frequency (hz) 0.1 1 10 100 0.1 1 10 100 1 10 100 1k 10k 100k 1m 10m 100m current noise (pa/ hz) input voltage noise (nv/ 12611-134 current noise v s range = 1.5v to 5v npn active figure 55. input voltage noise and current noise vs. frequency, v cm = +v s ? 0.5 v 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 102030405060708090100 load current (ma) v s = 2.5v g = +1 12611-043 ?40c +25c +125c +85c negative rail output saturation voltage (v) (?v s + v out ) figure 56. negative rail output saturation voltage (?v s + v out ) vs. load current for various temperatures 0.001 0.01 0.1 1 10 100 1000 0.1 1 10 100 1000 disabled output impedance (k ? ) frequency (mhz) 12611-144 v s = 2.5v disable = ?v s figure 57. disabled output impedance vs. frequency
data sheet ada4807-1/ada4807-2/ADA4807-4 rev. b | page 23 of 33 overdrive recovery and turn on/turn off times ?3 ?2 ?1 0 1 2 3 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 voltage (v) time (s) v in v out v s = 2.5v g = +1 r load = 1k ? 12611-041 figure 58. input overdrive recovery 0 200 400 600 800 1000 1200 1400 1600 1800 ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 turn on time (ns) temperature (c) v s = 5.0v v s = 2.5v v s = 1.5v g = +1 r load = 1k ? disable = ?v s to +v s 12611-033 figure 59. turn on time vs. temperature and supply ?3 ?2 ?1 0 1 2 3 output voltage (v) ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 input voltage (v) time (s) v in v out v s = 2.5v g = +2 r load = 1k ? 12611-044 figure 60. output ov erdrive recovery ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 temperature (c) 100 150 200 250 300 350 400 turn off time (ns) 12611-034 v s = 5.0v v s = 2.5v v s = 1.5v g = +1 r load = 1k ? disable = +v s to ?v s figure 61. turn off time vs. temperature and supply
ada4807-1/ada4807-2/ADA4807-4 data sheet rev. b | page 24 of 33 theory of operation the ada4807-1 / ada4807-2 / ADA4807-4 have a rail-to-rail input stage with an input range that goes 200 mv beyond either rail. a pnp transistor input pair is active for a majority of the input range, while an npn transistor input pair is active for the common-mode voltages within 1.3 v of the positive rail. the ada4807-1 / ada4807-2 / ADA4807-4 are fabricated using the analog devices, inc., third generation, extra fast complementary bipolar (xfcb) process resulting in exceptionally good distortion, noise, slew rate, and settling characteristics for 1 ma devices. given traditional rail-to-rail input architecture performance, the input 1/f noise is surprisingly low, and the current noise is only 0.7 pa/hz for a 3 nv/hz voltage noise. typical high slew rate devices suffer from increased current noise because of input pair degeneration and higher input stage current. the ada4807-1 / ada4807-2 / ADA4807-4 exceed current benchmark parameters given the performance of the xfcb process. the multistage design of the ada4807-1 / ada4807-2 / ADA4807-4 has excellent precision specifications, such as input drift, offset, open-loop gain, cmrr, and psrr. typical harmonic distortion numbers fall in the range of ?130 dbc for a 10 khz fundamental (see the distortion and noise section). this level of performance makes the ada4807-1 / ada4807-2 / ADA4807-4 the best choices when driving 18-bit precision converters. the ada4807-1 / ada4807-2 are optimized for a low shutdown current (4 a maximum), in the order of a few microamperes. in power sensitive applications, this can eliminate the use of a power fet and enable time interleaved power saving operation schemes. the rail-to-rail input stage is useful in many different applications. although the precision is reduced from input to input, many applications can tolerate this loss when the alternative is no functionality at all. the positive rail input range is indispensable for servo loops with a high-side input range the ada4807-1 / ada4807-2 / ADA4807-4 input operates 200 mv beyond either rail. internal protection circuitry prevents the output from phase inverting when the input range is exceeded. when the input exceeds a diode beyond either rail, internal electrostatic discharge (esd) protection diodes source or sink current through the input. differential drive from input stage q37 q47 q21 q20 q51 q27 q68 q44 q42 q48 q49 q50 q43 v out q38 i1 i2 c9 c5 i5 i4 r29 + + 12611-052 figure 62. differential drive from input stage q3 q2 q13 q17 q8 q14 q7 q11 q18 q4 + v s v in v ip q5 q9 ?v s output stage, common-mode feedback v bias1 v bias2 r4 r2 r1 r3 i1 5a i2 1.3v r5 12611-051 figure 63. simplified schematic
data sheet ada4807- 1/ada4807 - 2/ada4807 - 4 rev. b | page 25 of 33 disable circuitry when the disable pin is an option, a pull - up resistor is required if the logic leakage currents exceed 300 na . for a 10 v supply, p ulling the disable pin to below 6 .3 v turns the ada4807 - 1 / ada4807 - 2 off, which reduc es the supply current to 2.4 a. conversely, pulling the disable pin voltage to above 6.6 v enables the ada4807 - 1 / ada480 7 - 2 with a quiescent current of 1 ma. when the ada4807 - 1 / ada4807 - 2 device is disabled , its output enters a high impedance state. figure 64 and table 10 show the disable functionality over the complete supply range. 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 3 4 5 6 7 8 9 10 trigger vo lt age below +v s (v) power supp l y , v s (v) v th v on = v th +150mv v off = v th ?150mv 126 1 1-152 figure 64 . disable trigger voltage table 10 . threshold voltages for disabled and enabled modes mode +3 v +5 v +10 v 5 v +7 v/ ? 2 v enabled 1. 35 v 1.6 v 6 .6 v 1.6 v 3.6 v disabled 1.05 v 1. 3 v 6 .3 v 1.3 v 3. 3 v the output impedance decreases as the frequency increases. when disabled, a fo rward isolation of 120 db is achieved at 100 khz (see figure 22 ). esd clamps protect the disable pin, as shown in figure 65 . voltages be yond the power supplies cause these diodes to conduct. to avoid excessive current in the esd diodes, ensure that the voltag e to t he disable pin is not 0.7 v greater than the positive supply or th at it is not 0.7 v less than the negative supply. if an overvoltage condition is expected, limit the input current to less than 10 ma with a series resistor. input protec ti on the ada4807 - 1 / ada4807 - 2 / ada4807 - 4 are fully protected from esd events, withstandin g human body model esd events of 3 kv and c harged device model events of 1.25 kv with no measured performance degradat ion. the precision input is protected with an esd network between the power supplies and diode clam ps across the input device pair, as shown in figure 65 . f or differential voltages above approximately 1.2 v at room temperature and 0.8 v at 125 c, the diode clamps begin to conduct. too much current can cause damage due to excessive heating. if large d ifferential voltages must be sustained across the input termina ls, it is recommended that the current through the input clamps be limited to less than 10 ma. series input resistors sized appropriately for the expected differential overvoltage provide the needed protection. +inx esd esd ?v s +v s bias to the rest of the amplifier ?inx esd esd 126 1 1-054 notes 1. the inx pins are in on the ada4807-1, in1 and in2 on the ada4807-2, and in1 t o in4 on the ADA4807-4. figure 65 . input stage and protection diodes noise considerations figure 66 illustrates the primary noise contributors for the typica l gain configurations. the total output noise ( v n_out ) is the root sum square of all the noise contributions. r g r s i e p i e n + v ou t _e n ? r f ve n 4k t r s v n _ r s = 4k t r g v n _ r g = 4k t r f v n _ r f = 126 1 1-055 figure 66 . noise sources in typical gain configurations source resistance noise, amplifier input voltage noise, and the voltage noise from t he amplifier input current noise ( i n + r s ) are all subject to the noise gain term (1 + r f /r g ). calculate the output noise spectral density using the following equation: [ ] f n g g f n s n g f f out n r i ktr r r v r i ktrs r r ktr v ? + + ? ? ? ? ? ? ? ? + + + ? ? ? ? ? ? ? ? + + = k is boltzmanns constant. t is the absolute temperature in degrees kelvin. r f and r g are the feedback network resistances, as shown in figure 66. r s is the source resistance, as shown in figure 66. i n + and i n ? represent the amplifier input current noise spectral density in pa/hz. v n is the amplifier input voltage noise spectral density in nv /hz.
ada4807- 1/ada4807 - 2/ada4807 - 4 data sheet rev. b | page 26 of 33 applications information capacitive load d rive figure 67 shows t he schematic for driving large capacitive loads , and figure 68 shows the frequency response for a gain of +2 . note that the bandwidth decreases with larger capacitive loads (see figure 68) . figure 69 shows the required series resis tor (r series ) when limiting the peaking to 3 db for a range of load capacitors (c load ) at a gain of + 2. from figure 69 , no series resistors are necessary to maintain stability for larger c apacitors. r f r g r series v load r t 49.9 v out v in r load c load 126 1 1-056 figure 67 . schematic for driving l arge capacitive loads ?18 ?15 ?12 ?9 ?6 ?3 0 3 6 0.1 1 10 100 1000 normalized closed-loop gain (db) frequency (mhz) v s = 5v r load = 1k g = +2 v out = 70mv p-p 100nf, 0.5 10nf, 1.69 1nf, 10.5 15pf, 100 47pf, 82.5 470pf, 20 12611-155 figure 68 . frequency response for driving large capacitive loa ds , r f = r g = 249 12611-057 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 100 r series () c load (nf) figure 69 . required series resistor (r series ) vs . capacitive load (c load ) at 3 db p eaking low noise fet operationa l amplifier low noise amplifiers for photodiode, piezoelectric, and other instrumentation applications typically call for circuit paramete rs such as extremely high input impedance, low 1/f noise, or sub - picoamp bias currents that can be met only with a discrete amplifier design. the discrete amplifier shown in figure 70 uses a high - speed op amp preceded by a differential amplifier stage. this discrete config - uratio n is implemente d with dual matched jfets, which provide high input impedance and some initial gain , reducing the noise and precision specifications of the second stage. the low current consumption of the ada4807 - 1 / ada4807 - 2 / ada4807 - 4 , in addition to their precision and low noise characteristics, result s in a composite design with 7 ma of total supply current , 1.5 nv/hz noise at 1 khz, and 4 nv/hz noise at 10 hz. the unbalanced output impedance of the fets is negated by the use of an inverting amplifier cascode. the ada4807 - 1 / ada4807 - 2 / ada4807 - 4 are ideally suited for the cascode due to the ir rail - to - rail input structure , which results in excellent overload behavior of the overall discrete amplifier. using this cascode structure , the cmrr is greater than 100 db. a high output impedance current source is also needed to maintain the cmrr of the discr ete amplifier. an adr510 maintains a precise current over the supply voltage , and the low collector capacitance of the pmp4201 results in a balanced and predictable slew rate beha vior. this is shown in figure 71 with a 0.4 v p - p input and a 4 v p - p output with a gain of 10. figure 72 sh ows o utput referred total harmonic distortion plus noise ( thd + n ) for a gain of 10.
data sheet ada4807-1/ada4807-2/ADA4807-4 rev. b | page 27 of 33 ada4807-1/ ada4807-2/ ADA4807-4 ada4807-1/ ada4807-2/ ADA4807-4 + +5v +5v +5v v out c7 27pf c9 2pf c0 20pf v os trim rb 100 ? r12 100 ? r3 1k ? r4 5k ? r13 100 ? r0 100 ? r1 10 ? r2 100 ? r6 5k ? r7 200? v os trim v? ?5v v+ qn0 qn1 1/2 lsk489 1/2 pmp4201 adr510 1/2 pmp4201 1/2 lsk489 ?5v ?5v ? + ? 12611-068 figure 70. low noise fet oper ational amplifier schematic ch1 200mv ch2 1v m100ns a ch1 0v 1 2 ? 12611-069 figure 71. pulse response, g = 10, 4 v p-p output ? 60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 ?105 ?110 100 1k 10k 20k distortion (%) frequency (hz) 12611-071 figure 72. 8 v p-p output, thd + n for g = 10, r load = 600 power mode adc driver one of the merits of a sar adc, such as the ad7980 , is that its power scales with the sampling rate. this power scaling makes sar adcs very power efficient, especially when running at a low sampling frequency. however, the adc driver used with the sar adc traditionally consumes constant power regardless of the sampling frequency. figure 73 illustrates a method by which the quiescent power of the adc driver can be reduced by 95% while still maintaining the input signal to the adc. both the ada4807-1 / ada4807-2 / ADA4807-4 and the ad8603 are rail-to-rail input and output (rrio) amplifiers and can operate on a single 5 v analog supply. connecting the ad8603 in parallel with a sharing resistor allows the ada4807-1 / ada4807-2 / ADA4807-4 to be powered down, reducing the total supply current for the driver from 1 ma to 50 a. the sampling frequency of the ad7980 can then be reduced to match the power consumption of the ad8603 . with the ada4807-1 / ada4807-2 / ADA4807-4 powered on, the snr and thd are 84.1 db and ?100.3 db for a 3 v p-p, 1 khz input and a 4.096 v reference. the snr and thd degrade to 81.4 db and ?77.3 db for the same input signal in the low power mode when only the ad8603 is on. one issue with this method is that the reference and reference buffer power do not scale with the adc or the driver. this makes this configuration most useful in multichannel systems where the reference can be reused across many inputs. alternately, the reference buffer can be scaled in the same fashion as the input driver; however, the reference itself must remain on in any of the modes.
ada4807-1/ada4807-2/ADA4807-4 data sheet rev. b | page 28 of 33 ad7980 ref in+ in? gnd adr4540 + ? ad8603 + ? 5v 5v c4 0.1f c3 10f c2 0.1f c1 2.7f r10 22 ? r11 49.9 ? 5v 5v lp mode v in + ? 12611-070 ada4807-1/ ada4807-2/ ADA4807-4 ada4807-1/ ada4807-2/ ADA4807-4 figure 73. dual power mode adc driver adc driving the ada4807-1 / ada4807-2 / ADA4807-4 can be used in adc driving applications. figure 74 is a simplified schematic of the ada4807-1 / ada4807-2 / ADA4807-4 driving an 18-bit differential adc, the ad7982 , in a fully differential signal chain. this configu- ration results in an effective number of bits (enob) of 15.7; results are shown in figure 75. ada4807-1/ ada4807-2/ ADA4807-4 ada4807-1/ ada4807-2/ ADA4807-4 v in+ 20 ? 2.7nf 2.7nf 20 ? v in? adc in? in+ 12611-275 figure 74. schematic for driving the ad7982 , +v s = +7 v, ?v s = ?1 v 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 201816141210 86420 frequency (khz) f s = 200ksps f in = 1khz snr = 96.6db thd = ?111.5db sfdr = ?112.3db sinad = 96.5db 12611-075 amplitude (db) figure 75. fft for driving a diffe rential converter, ?0.5 dbfs figure 76 shows the ada4807-1 / ada4807-2 / ADA4807-4 configured to convert a single-ended to differential signal and drive an 18-bit adc. this configuration results in an enob of 15.3. the fft is shown in figure 77. adc ref 2 in? in+ 20 ? 2.7nf 2.7nf 20 ? 1k ? 1k ? v in 12611-276 ada4 807-1/ ada4 807-2/ ada4 807-4 ada4807-1/ ada4807-2/ ADA4807-4 figure 76. schematic for driving the ad7982 differential converter from a single-ended input signal, +v s = +7 v, ?v s = ?1 v 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 2018 1614 1210 86420 frequency (khz) f s = 200ksps f in = 1khz snr = 94.5db thd = ?110.3db sfdr = ?111.1db sinad = 94.4db 12611-077 amplitude (db) figure 77. fft for driving a single-ended input signal into a differential converter
data sheet ada4807- 1/ada4807 - 2/ada4807 - 4 rev. b | page 29 of 33 adc driving with dynamic power s caling in power sensitive applications, the ada4807 - 1 / ada4807 - 2 can be switched on prior to the adc turning on. figure 78 shows the timing diagram for dynamically po wer scaling the ada4807 - 1 / ada4807 - 2 with the ad7982 configuration shown in figure 79 . t he falling edge of the disable signal must align with the rising edge of the conv signal of the adc to obtain a clean data acquisition. figure 79 gives t he fft for driving a fully differential signal chain with a 1.2 s on time a s shown in figure 78. with this method, the ada4807 - 1 / ada4807 - 2 quiescent current (per amplifier) is reduced from 2 ma to 0.25 ma. figure 81 gives the fft for dynamically power scaling a single - ended input signal chain into a differential adc with a 4 s on time as shown in figure 80. this configuration results in a quiescent current reduction of 20% . ch1 2v ch2 2v m1s a ch1 2.56v 1 2 conv disable 126 1 1-278 figure 78 . dynamic p ower s caling t iming di agram for d riving a f ully d ifferential s ignal c hain i nto a d ifferential adc ( ad7982 ) 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 20 18 16 14 12 10 8 6 4 2 0 frequenc y (khz) f s = 200ksps f in = 1khz snr = 96.7db thd = ? 1 10.9db sfdr = ? 11 1.8db sinad = 96.6db 126 1 1-079 amplitude (db) figure 79 . f ft for driving a differential converter using dynamic power scaling , 0.5 dbfs, o n t ime of 1.2 s , for the schematic s hown in figure 74 ch1 2v ch2 2v m1s a ch1 2.56v 1 2 conv disable 126 1 1-078 figure 80 . dynamic power scaling timing diagram for driving a s ingle - e nded i nput signal chain into a differential adc ( ad7982 ) 0 amplitude (db) ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 20 18 16 14 12 10 8 6 4 2 0 frequenc y (khz) f s = 200ksps f in = 1khz snr = 94.7db thd = ?107. 1 1db sfdr = ?108.8db sinad = 94.4db 126 1 1-080 figure 81 . f ft for driving a single - ended to differential converter using dynamic power scaling , 0.5 dbfs, on time of 4 s, f or the schematic shown in figure 76
ada4807- 1/ada4807 - 2/ada4807 - 4 data sheet rev. b | page 30 of 33 layout, grounding, a nd by p assing the ada4807 - 1 / ada4807 - 2 / ada4807 - 4 are high speed device s . realizing their superior performance requires att ention to the details of high speed printed circuit board ( pcb ) d esign. the first requirement is to use a multilayer pcb with solid groun d and power planes that cover as much of the board area as possible. bypass each power supply pin directly to a nearby ground plane , as close to the device as possible. use 0.1 f high frequency ceramic chip capacitors. provide low frequency bulk bypassing using 10 f tantalum capacitors from each supply to ground. stray transmission line capacitance in combination with p ackage parasitics can potentially form a resonant circuit at high frequencies, resulting in excessive gain peaking or possible oscillation. signal routing must be short and direct to avoid such parasitic effects. provide symmetrical layout for complementar y signals to maximize balanced performance. use radio frequency transmission lines to connect the driver and receiver to the amplifier. minimize stray capacitance at the input and output pins by clearing the underlying ground and low impedance planes near these pins . if the driver and receiver are more than one - eighth of the wavelength from the amplifier, minimize the signal trace widths. this nontransmission line configuration requires clearing of the underlying and adjacent ground and low impedance planes near the signal lines.
data sheet ada4807-1/ada4807-2/ADA4807-4 rev. b | page 31 of 33 outline dimensions 1.30 bsc compliant to jedec standards mo-203-ab 1.00 0.90 0.70 0.46 0.36 0.26 2.20 2.00 1.80 2.40 2.10 1.80 1.35 1.25 1.15 072809-a 0.10 max 1.10 0.80 0.40 0.10 0.22 0.08 3 12 4 6 5 0.65 bsc coplanarity 0.10 seating plane 0.30 0.15 figure 82. 6-lead thin shrink small outline transistor package [sc70] (ks-6) dimensions shown in millimeters compliant to jedec standards mo-178-ab 10 4 0 seating plane 1.90 bsc 0.95 bsc 0.60 bsc 65 123 4 3.00 2.90 2.80 3.00 2.80 2.60 1.70 1.60 1.50 1.30 1.15 0.90 0 .15 max 0 .05 min 1.45 max 0.95 min 0.20 max 0.08 min 0.50 max 0.30 min 0.55 0.45 0.35 pin 1 indicator 12-16-2008-a figure 83. 6-lead small outline transistor package [sot-23] (rj-6) dimensions shown in millimeters
ada4807-1/ada4807-2/ADA4807-4 data sheet rev. b | page 32 of 33 compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b figure 84. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters 2.48 2.38 2.23 0.50 0.40 0.30 10 1 6 5 0.30 0.25 0.20 pin 1 index area seating plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pad 3.10 3.00 sq 2.90 p i n 1 i n d i c a t o r ( r 0 . 1 5 ) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 0 2-05-2013-c top view bottom view 0.20 min figure 85. 10-lead lead frame chip scale package [lfcsp_wd] 3 mm 3 mm body, very very thin, dual lead (cp-10-9) dimensions shown in millimeters
data sheet ada4807-1/ada4807-2/ADA4807-4 rev. b | page 33 of 33 compliant to jedec standards mo-153-ab-1 061908-a 8 0 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 0.75 0.60 0.45 coplanarity 0.10 seating plane figure 86. 14-lead thin shrink small outline package [tssop] (ru-14) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding ada4807-1aksz-r2 ?40c to +125c 6-lead thin shrink small outline transistor package [sc70] ks-6 h3j ada4807-1aksz-r7 ?40c to +125c 6-lead thin shrink small outline transistor package [sc70] ks-6 h3j ada4807-1arjz-r2 ?40c to +125c 6-lead small o utline transistor package [sot-23] rj-6 h3j ada4807-1arjz-r7 ?40c to +125c 6-lead small o utline transistor package [sot-23] rj-6 h3j ada4807-2acpz-r2 ?40c to +125c 10-lead lead frame chip scale package [lfcsp_wd] cp-10-9 h3s ada4807-2acpz-r7 ?40c to +125c 10-lead lead frame chip scale package [lfcsp_wd] cp-10-9 h3s ada4807-2armz ?40c to +125c 8-lead mini small outline package [msop] rm-8 h3s ada4807-2armz-r7 ?40c to +125c 8-lead mini small outline package [msop] rm-8 h3s ADA4807-4aruz ?40c to +125c 14-lead thin shrink small outline package [tssop] ru-14 ADA4807-4aruz-r7 ?40c to +125c 14-lead thin shrink small outline package [tssop] ru-14 ada4807-1aksz-ebz evaluation board for 6-lead sc70 ada4807-1arjz-ebz evaluation board for 6-lead sot-23 ada4807-2acpz-ebz evaluation board for 10-lead lfcsp_wd ada4807-2armz-ebz evaluation board for 8-lead msop ADA4807-4aurz-ebz evaluation board for 14-lead tssop 1 z = rohs compliant part. ?2014C2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d12611-0-9/15(b)

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